Microprocessor
without Interlocked Pipelined Stages (MIPS)
Introduction
Introduction
registers
access with $t0 etc
li load immediate
li $t1, 8 (loads 8 into t1)
add $t0, $t0, $t1 (add t1 and t0 and put in t0)
NA: move, li, la and others and pseudo instructions